Welcome Reception

Evening Panel

Opening Greeting by Peilin Song, Sule Ozev

Keynote Speech by Robert Madge

Invited Talk by Professor Mani Soma, University of Washington
"High-frequency on-chip measurements: Challenges and Approaches"

Abstract
On-chip test methods for high-frequency (2 - 50 GHz) systems have been studied as a possible alternative for existing costly ATE-based tests. Integral to any test method is measurement: what do we measure so that either a parameter of interest can be estimated or a final Pass-Fail decision can be inferred? What is the influence of the measuring circuit itself on the quantity being measured? This presentation outlines the challenges in on-chip GHz measurements and investigates current and possible approaches. We will show that classical radio-frequency methods are not adaptable for on-chip measurements, and there must be a dramatic shift in test thinking before we succeed in solving this difficult yet very interesting problem.

"System-Level BIST for Programmable I/O Buffers in FPGAs, SoCs," by Lee Lerner, Sudheer Vemula and Charles Stroud, Auburn University.

"Identification of Failing Clock Domains in Very High-Speed System-on-Chip Circuits," by Chunsheng Liu, Krishnendu Chakrabarty and Vikram Iyengar, University of Nebraska at Lincoln, IBM Corp., and Duke University.

"Test Power Reduction in SoC Memory BIST," by Yuejian Wu, Nortel.

"Analysis, Test of a Spectral, Mixed Signal BIST Technique for Systems on a Chip Applications," by John Emmert, Jason Cheatham, Harold Axtell, Robert Kertis, Vladimir Sokolov and Gregory Rash, Wright State University, Mayo Clinic.

"Performance Verification of High-Performance ASICs Using At-Speed Structural Test," by Vikram Iyengar, Theo Anemikos, Bob Bassett, Mike Degregorio, Rudy Farmer, Gary Grise, Mark Johnson, Phil Stevens, Mark Taylor and Frank Woytowich, IBM Corp.

"Phase Delay in MAC-based Analog Functional Testing in Mixed-Signal Systems," by Jie Qin, Charles Stroud and Foster Dai, Auburn University.

"Jitter in Voltage Control Oscillator Due to Internal, External Power Supply Noise," by Charles Chiu and Tian Xia, University of Vermont.

"Automated Calibration of Phase Locked Loop with On-Chip Jitter Test," by Tian Xia, Stephen Wyatt and Rupert Ho, University of Vermont.

"Design of Time Gated Multi-Frequency Wrapper Architecture for Faster-than-at-speed Delay Test," by Dan Zhao and Unni Chandran, University of Louisiana.

"A Novel Fault-Recovery method for Transient pulses, Signal Delays," Aditya Jagirdar, Roystein Oliveira and Tapan J. Chakraborty, Rutgers University and Lucent Technologies.

"A Case Study of IR-drop Effects During Faster-than at-Speed Delay Test," by Nisar Ahmed, Mohammad Tehranipoor and Vinay Jayaram, University of Maryland at Baltimore County, Texas Instruments.

"All-Digital Built-in Delay Measurement Circuit," Ching-Hwa Cheng, De-Sheng Chen, Wen-Jui Chang and Chih-Liang Chen, Feng-Chia University Taiwan, R.O.C.

"Built-In Current Sensors for IDDQ, IDDT Testing," by Chuen-Song Chen, Jien-Chung Lo and Tian Xia, University of Rhode Island and University of Vermont.

"BIST of Logic, Memory Resources in Virtex-4 FPGAs," by Sachin Dhingra, Daniel Milton and Charles Stroud, Auburn University.

"A BIST Approach for Detection, Diagnosis of FPGA Interconnect Faults," by Jack Smith, Tian Xia and Charles Stroud, University of Vermont and Auburn University.

"High-Level Test Generation for Gate-Level Fault Coverage," by Nitin Yogi and Vishwani D. Agrawal, Auburn University.

"An Analysis of Defect Detection, Site Observation Counts for Weighted Random Patterns, Compact Test Pattern Sets," by Jennifer Dworak, Brown University.

"Using Limited Dependence Sequential Expansion for Decompressing Test Vectors," Avijit Dutta and Nur A. Touba, University of Texas at Austin.

"A Novel Framework for Functionally Untestable Transition Fault Avoidance during ATPG," Jeremy Lee, Nisar Ahmed, Mohammad Tehranipoor, Vinay Jayaram and Jim Plusquellic, University of Maryland at Baltimore County, Texas Instruments.

"Wide-TAP An Architecture for Test Vector Depth Reduction," by Scott Erlanger and Dilip K. Bhavsar, Intel Corp.

"Fault Models for Threshold Logic Circuits Based on Resonant Tunneling Diodes," Weidong Kuang and Peiyi Zhao, University of Texas – Pan American, Chapman University.

"Realistic Resistive Bridging Faults Simulation Using SPICE Models," Marius Marcu and Mircea Vladutiu, University of Timisoara, Romania.

"Triangulating to a Defect's Physical Coordinates Using Multiple Supply Pad IDDQs: Test Chip Results," by Jim Plusquellic, Dhruva Acharyya, Mohammad Tehranipoor and Chintan Patel, University of Maryland, Baltimore County.

"Test Time, Defect Map Analysis of PLA, LUT-Based Nano-Architectures," by Reza M.P. Rad and Mohammad Tehranipoor, University of Maryland, Baltimore County.

"The Wireless Sensor Tissue: A Network of Wireless Sensor Nodes using Cellular Mechanisms for Autonomous Distributed Fault Tolerance," by Johnny Bolano, Oghenetejiri Eruotor, Yonathan Nerie, Kushal Datta, Arindam Mukherjee and Arun Ravindran, University of North Carolina at Charlotte.

"VIVO: A Biology-inspired Self-Repairable Distributed Fault Tolerant Design Methodology with Efficient Redundancy Insertion Technique," by Kushal Datta, Ravi Karanam, Jong-Ho Byun, Arindam Mukherjee, Bharatkumar Joshi and Arun Ravindran, University of North Carolina at Charlotte.

"A Soft Error Tolerant, Low Overhead TMR Design for Flip Flops," by Roystein Oliveira, Aditya Jagirdar and Tapan J.Chakraborty, Rutgers University and Lucent Technologies.